Many memory circuits are arranged in a plurality of memory banks. Typically, each of the memory banks comprises memory cells accessible by word lines and bit lines arranged in a two-dimensional rectangular or square array. Such memory circuits may include common bit lines, often referred to as global bit lines, selectively coupled to corresponding bit lines of the memory banks. A control circuit is typically provided in such memory circuits for receiving an input address associated with a selected memory cell to be accessed. Based on the input address, the control circuit selects the memory bank to which the selected memory cell pertains, selects the word line coupled to the memory cell, and causes the data in the selected memory cell to be outputted to a corresponding global bit line.
Typically, each memory bank includes a circuit, sometimes referred to a local data path (LDP), configured to transfer the data from the bit line associated with the selected memory cell to a corresponding global bit line. The speed on which that data is able to be transferred to the global bit line depends on the capacitive and resistive loading on the global bit line. If the memory circuit includes many memory banks, there may be many LDP circuits coupled to each global bit line. Each LDP circuit produces a capacitive and resistive load on the corresponding global bit line.
Accordingly, there is a need to reduce the capacitive and resistive loading of each global bit line in order to improve the speed on which data may be outputted by the memory circuit. Additionally, there is a further need to reduce the size of the integrated circuit area needed to implement all of the LDP circuits of a memory circuit.